Core Operator for Cracking Banking Encryption Runs on Over 100 Qubits for the First Time

Neutral Atoms

On September 24, 2026 (Beijing Time), Infleqtion announced at the 2026 Global Quantum Conference that its Sqale neutral-atom QPU (quantum processing unit) successfully prepared 30 entangled logical qubits using 80 physical qubits, fulfilling its annual technology roadmap commitment^[8][9]. In terms of technical metrics, the system achieved a physical-to-logical encoding efficiency of 2.67:1. However, moving toward practical fault tolerance still faces the physical constraint of neutral-atom system cycle repetition rates of only 1 to 10 Hz, and crosstalk mitigation during mid-circuit measurements requires ongoing optimization. This progress directly reduces the hardware overhead required for the neutral-atom roadmap to achieve medium-scale fault-tolerant systems, and the company is advancing toward 100 logical qubits while developing quantum applications with customers^[8][9].

Trapped Ions

The NVIDIA Accelerated Quantum Research Center has selected IonQ's Superion 256 quantum computer as its first on-premises deployed QPU, directly interfacing with GB200 NVL72 supercomputing racks via NVQLink (a dedicated electro-optical interconnect protocol) to build a hybrid hardware architecture^[28]. The system will establish an ultra-low-latency communication link between the 256-physical-qubit trapped-ion hardware and classical computing nodes, combining IonQ's error correction technology to accelerate financial risk management and drug molecular modeling. Although its physical qubit count reaches 256, it has not yet been disclosed whether its all-to-all two-qubit gate fidelity matches the commercial system record of 99.921% held by Quantinuum Helios, and the additional time overhead caused by multi-ion shuttling and transport remains the primary bottleneck for scaling to deeper circuits. The collaboration aims to advance quantum-GPU architectures and hybrid software frameworks for applications in finance, materials science, and drug discovery^[28].

IonQ CEO Niccolo de Masi publicly stated that the rapid evolution of quantum error correction technology will bring fault-tolerant quantum systems to a cost level affordable for governments and thousands of enterprises within two years^[13]. This assertion accelerates the prevailing industry timeline of 2030 to 2033 for fault tolerance by 4 to 6 years; however, currently across the entire industry, only Google's Willow chip has demonstrated a closed-loop surface code with an error suppression factor reaching 2.1. The trapped-ion roadmap has yet to publish independent third-party replication data for single-system thousand-qubit-scale error correction. The projection of achieving low-cost commercial fault tolerance within two years exceeds the best published evolutionary pace and remains to be independently verified. Such aggressive expectations directly elevate capital market valuation anchors for trapped-ion commercialization, but also exacerbate the risk of overdrawn credibility if viable logical machines fail to ship before 2028^[13].

IonQ formally signed a deployment agreement with Florida International University (FIU) in Miami to install a Superion 256 quantum computer on-site at the university, establishing its status as IonQ's flagship academic partner^[52]. This move introduces a commercial hundred-qubit-class trapped-ion system to a regional university research ecosystem for the first time, accelerating the interdisciplinary convergence of quantum computing with local frontier research in Florida^[52].

Superconducting Route

A research team has designed and experimentally validated a high-fidelity LRU (leakage reduction unit) for superconducting quantum chips, which operates in parallel with quantum measurements on transmons, eliminating non-computational state leakage without pausing the system^[33]. This scheme completely eliminates the nanosecond- to microsecond-scale latency wasted when superconducting chips must periodically pause and reset due to the accumulation of non-computational energy states in error correction cycles. Compared with the measurement-and-reset mechanisms currently employed in systems such as Google's Willow, this hardware unit suppresses correlated errors while imposing zero additional time overhead on the two-level computational subspace; however, overall system coherence remains constrained by coherence time fluctuations caused by two-level system (TLS) defect fluctuations within superconducting materials. This design provides superconducting hardware designers with a ready-to-use reference module for leakage mitigation^[33].

Following recent reports on the launch of the Microsoft Quantum Makerspace, latest developments show that Fermi National Accelerator Laboratory (Fermilab) has joined the makerspace at the University of Maryland Discovery District as an inaugural partner, extending its Quantum Instrumentation Control Kit (QICK) into a standardized tool across heterogeneous hardware^[4]. This collaboration bridges national-laboratory-grade high-performance RF control and readout tools with Microsoft's topological and fault-tolerant software ecosystem, lowering engineering barriers for external hardware teams developing proprietary low-level control drivers^[4].

Quantum control provider Quantum Machines has adopted AMD high-performance computing chips to build classical underlying infrastructure, achieving real-time integration between nanosecond-level qubit control precision and millisecond-level classical computing workflows^[31]. This architecture bridges the computing gap between ultra-fast pulse feedback prior to quantum decoherence and complex decoding algorithms, accelerating the upgrade of control systems from discrete chassis to high-density integrated modules^[31].

Semiconductor Spin and Photonics

The Defense Advanced Research Projects Agency (DARPA) Quantum Benchmarking Initiative (QBI) announced a shortlist of nearly 20 selected companies, including developers of silicon spin qubits based on MOS (metal-oxide-semiconductor) structures, with the goal of driving the development of fault-tolerant machines before 2033^[36]. While physical qubit counts in the MOS spin roadmap are currently generally under 12 qubits, its core advantage lies in its ability to leverage mature 300 mm wafer foundry lines; this signifies that the silicon-based roadmap has been officially integrated into national strategic priority tracks, which will accelerate semiconductor foundry support for cryogenic spintronic devices^[36].

Quantum Source unveiled a composite architecture blueprint combining atoms and photons, specifically aimed at overcoming hardware connectivity barriers in quantum interconnects and fault-tolerant computing^[39]. By reducing photon loss overhead through a hybrid topology, the technology provides a novel physical implementation scheme for long-distance quantum communication repeater nodes and distributed multi-core chip connectivity^[39].

Quantum software and control company Q-CTRL utilized a novel convolutional compilation strategy to successfully execute a Quantum Fourier Transform (QFT) across up to 100 qubits on the IBM Heron 156-qubit superconducting chip, setting a record for the largest-scale execution of a functional QFT on quantum hardware^[27]. By employing an identity-based cancellation mechanism and introducing a single ancilla qubit, this compilation strategy completely eliminated the additional SWAP gate routing overhead on hardware with linear nearest-neighbor topology^[27]. This achievement advances the scaled validation of core cryptographic cryptanalysis operators (such as Shor's algorithm) on real noisy physical hardware, providing high-precision empirical benchmarks for subsequent algorithm teams evaluating actual codebreaking resource overheads^[27].

An independent cross-benchmark test on the IBM Heron 156-qubit chip demonstrated that in evaluating commercial quantum error management tools, solutions from both Q-CTRL and Qedma's QESEM substantially reduced computational errors, outperforming IBM's native Qiskit Runtime environment in measurement precision^[26]. The benchmark results established a clear trade-off profile: Qedma traded higher QPU execution runtime overhead for industry-leading suppression precision, while Q-CTRL achieved a balance between execution time and error reduction ratio^[26]. This evaluation breaks the sole monopoly of OEM default compilation software, prompting enterprise users to select third-party specialized error management tools tailored to their latency and precision budgets^[26].

Fault-tolerant architecture design firm QC Design released a white paper demonstrating that its dedicated Meridian automated fault-tolerant architecture design system reduced logical error rates to less than one-tenth of existing published solutions and general-purpose optimization algorithms across more than 100 design tasks^[51]. This result indicates that specialized search strategies incorporating quantum error correction topological features offer significant generational advantages in surface code and low-density parity-check (LDPC) code routing, driving quantum chip design from manual topological derivation into an era of dedicated electronic design automation (EDA)^[51].

Distributed quantum networking company memQ publicly released its open-source distributed quantum compiler, DQC, on GitHub, supporting the decomposition and optimization of complex quantum circuits across multi-QPU interconnect networks and distributed nodes^[48]. This tool fills the void of standardized open-source compilers for cross-chip collaborative computing, significantly lowering the development barrier for multi-institutional consortiums building distributed computing testbeds^[48].

Quantum sensing and precision timing company Mesa Quantum announced the closing of an $11.8 million funding round led by Playground Global^[47]. The capital will be used to accelerate the company's transition from chip-scale core components to scaled mass production of fully packaged quantum timing systems. Its business model primarily targets precise clock synchronization markets in GNSS-denied defense and air defense environments, high-frequency telecommunications base stations, and multinational financial data centers, signaling that the quantum precision measurement sector is entering an engineered volume delivery phase^[47].

Leading neutral-atom vendor Pasqal released its financial report for the first half of 2026, reporting total revenue of €4.9 million, a year-over-year increase of 14%, with QPU-related quantum cloud computing service revenue surging 34% year-over-year^[34]. Concurrently, Pasqal received the European Innovation Council (EIC) Fund Award at the European Deep Tech Summit held in Luxembourg, reflecting its steady expansion cadence backed by European sovereign capital; service revenues derived from compute-time leasing and collaborative algorithm development have become the most resilient cash-flow pillar in this sector^[34][53].

Nasdaq-listed additive electronics company QTREX Quantum released its H1 2026 results, achieving record revenue of $1.55 million in its additive manufactured electronics business targeting quantum infrastructure^[55]. This figure indicates that upstream critical components such as cryogenic coaxial cabling and 3D packaging for quantum computing have established an initial commercial self-sustaining loop, with further specialization across the supply chain^[55].

UK-based Oxford Quantum Circuits (OQC) announced the appointment of former Chief Technology Officer Simon Phillips as Chief Product Officer (CPO), with full responsibility for productization strategy and enterprise hardware delivery^[16][49]. This leadership appointment indicates that the veteran European superconducting hardware team is shifting core resources from early prototype technical validation toward standardized rack delivery and enterprise B2B sales execution^[16][49].

Bifrost Electronics, a manufacturer of underlying electronics hardware for quantum computing, appointed veteran hardware entrepreneur Doug Campbell as its new Chief Executive Officer^[50]. The move aims to leverage his supply chain experience in commercial electronics and aerospace hardware to accelerate volume manufacturing of cryogenic high-frequency readout and control modules required for superconducting and spin-based systems^[50].

In the $2 million Q4Bio Global Biopharma Algorithm Challenge, five of the six finalist teams chose IBM quantum hardware to conduct algorithm validation^[37]. This hardware preference in the competition indicates IBM's leading ecosystem penetration in life sciences and early-stage drug molecular screening, accelerating its lock-in of biocomputing software development standards over the next 3 to 5 years^[37].

A cryptography research team disclosed a new technique capable of directly bypassing 1024-bit RSA public-key encryption without factoring large integers, reducing the classical computational cost required to break the key from an estimated 500,000 to 1,000,000 CPU core-years down to 1,380 CPU core-years^[7]. Although the attack still demands thousand-core-scale classical computing resources, it reduces cracking complexity by more than 360-fold compared to the traditional general number field sieve, posing a substantive threat to classical asymmetric cryptographic defenses within the realm of purely classical compute^[7]. This advance significantly shortens the grace period for migrating legacy financial communications and IoT systems to post-quantum cryptography (PQC) standards, forcing security organizations to accelerate the deprecation of 1024-bit public-key protocols^[7].

Nature npj Quantum Information published research on a completely modulator-free QKD (quantum key distribution) transmitter architecture^[15]. This design entirely eliminates conventional high-speed electro-optic modulators, removing device insertion loss and potential vulnerabilities to high-frequency electromagnetic side-channel leakage, thereby providing a new paradigm for developing highly integrated, eavesdropping-resistant chip-scale metropolitan quantum secure communication nodes^[15].

The European Telecommunications Standards Institute (ETSI) published technical report ETSI TR 104 171, explicitly detailing the vulnerabilities of QRNGs (quantum random number generators) in practical engineering implementations and providing implementation guidelines to prevent side-channel information leakage^[38]. The report emphasizes that non-ideal detector responses or parasitic emissions could allow adversaries to infer output sequences, providing implementation guidance for side-channel attack countermeasures in global cryptographic hardware compliance evaluations^[38].

An IonQ research team used QCBMs (quantum Circuit Born Machines) and trapped-ion chips to successfully identify subtle surface changes across massive datasets of synthetic aperture radar (SAR) satellite imagery from Capella Space^[12]. Conducted on noisy physical hardware, the experiment demonstrated the sensitivity advantage of quantum probability distribution models in characterizing multi-temporal radar features, providing a practical hybrid-compute validation benchmark for Earth observation and disaster prevention remote-sensing analysis^[12].

Researchers at EPFL (École Polytechnique Fédérale de Lausanne) successfully detected quasiparticles carrying one-quarter of an electron charge in fractional quantum Hall effect experiments^[41]. This measurement adds crucial experimental evidence for the existence of non-Abelian anyon states, solidifying the physical foundation for building hardware-level topologically protected qubits, though engineering device realization still requires prolonged fundamental exploration^[41].

A novel vertical quantum sensor has been developed, enabling fine imaging of microscopic magnetic fields and current paths within topological materials and unconventional superconductors at nanoscale spatial resolution^[18]. The device provides high-precision analytical capabilities for probing microscopic material defects and localized leakage currents in superconducting thin films for future quantum computing chips^[18].

The Tezos public blockchain technical team officially launched its quantum-resistant experimental testnet, Quantumnet, enabling validator nodes to execute quantum-resistant signatures and multi-node verification stress tests in a live blockchain environment^[54]. The testnet provides a production-grade proving ground for decentralized ledgers to prepare against future quantum computational attacks^[54].

1. Information Security and PKI Operations Teams affected by ^[7][38][54]: With the computational threshold for cracking 1024-bit RSA shrinking by hundreds of times and ETSI formally establishing standards for QRNG side-channel vulnerabilities, classical static asymmetric cryptographic defenses have effectively been breached. Enterprises must conduct comprehensive audits of legacy certificate systems within the year and initiate migration validation toward quantum-resistant hybrid certificates; the next step is to closely monitor compliance deadlines set by international standards bodies for deprecating legacy asymmetric public keys.
2. Neutral-Atom and Fault-Tolerant Hardware R&D Teams affected by ^[8][9][33]: Infleqtion realized 30 entangled logical qubits with an efficient physical-to-logical encoding ratio of 2.67:1, while the superconducting domain validated in-situ leakage reduction units with zero pause time, significantly enriching available engineering tools for suppressing error accumulation at the hardware layer. Next steps should focus closely on the repetition-rate limitations of neutral-atom platforms in deeper circuits, as well as cross-chip uniformity of superconducting leakage mitigation schemes across hundred-qubit arrays.
3. Heterogeneous Supercomputing Center and Cloud Platform Architects affected by ^[28][31][48]: Full IonQ systems directly interfacing with NVIDIA flagship racks via dedicated ultra-high-speed electro-optical interconnect protocols disrupt the traditional loosely coupled cloud API interaction paradigm, while the open-sourcing of distributed compilation tools further lowers cross-node coordination barriers. Next steps warrant tracking empirical end-to-end speedup benchmark data from this rack-scale hybrid architecture in real-world deployment scenarios across major pharmaceutical enterprises.
4. Algorithm Developers and Biopharmaceutical Researchers affected by ^[26][27][37]: Zero-routing-overhead execution of 100-qubit Quantum Fourier Transforms confirms the power of specialized compilation strategies in extracting maximum performance from underlying hardware, while independent third-party benchmarks have established a precision-versus-time coordinate system for commercial error mitigation/management software. Next steps require closely monitoring algorithm teams developing commercially viable inverted prototypes for biopharmaceutical macromolecular simulations on hundred-qubit physical machines.

Hardware competition is rapidly shifting from merely stacking physical qubit counts to evaluating error-correction encoding efficiency and system-level heterogeneous integration. Whether through the high-density compression of 30 logical qubits encoded into 80 physical qubits on neutral-atom platforms, or non-pausing measurement designs that eliminate state leakage in the superconducting domain, the industry consensus has clearly coalesced around maximizing the lifetime and performance of logical computing units at minimal physical resource overhead. Concurrently, trapped-ion systems directly interfacing with supercomputing racks via proprietary interconnect protocols demonstrate that the future computing topology is decidedly not standalone, isolated machines, but tightly coupled co-processors embedded within existing high-performance computing clusters. Refining engineering interconnects and software stacks has thus become the critical battleground for claiming the high ground in commercial ecosystems.

In cybersecurity defense, the risk of cryptographic compromise is transitioning from distant theoretical projections to imminent technical reality. The drastic collapse in classical computing overhead required to break 1024-bit legacy public keys, combined with mandatory standards from international organizations addressing physical random number side-channel vulnerabilities, has thoroughly invalidated passive strategies that postpone defense until fault-tolerant hardware matures. Government and enterprise clients, along with financial institutions, are being forced to accelerate seamless transitions from legacy cryptographic systems to post-quantum cryptography and hardware-grade side-channel countermeasures; the comprehensive restructuring of defense-in-depth architectures has entered an irreversible execution window.